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| NCP1651 Product Preview Single Stage Power Factor Controller The NCP1651 is an active, power factor correction controller that can operate over a wide range of input voltages. It is designed for 50/60 Hz power systems. It is a fixed frequency controller that can operate in continuous or discontinuous conduction modes. The NCP1651 provides a low cost, low component count solution for isolated ac- dc converters with mid- high output voltage requirements. The NCP1651 eases the task of meeting the IEC1000-3-2 harmonic requirements for converters in the range of 50 W - 250 W. The NCP1651 drives a flyback converter topology to operate in continuous/discontinuous mode and programs the average input current to follow the line voltage in order to provide unity power factor. By using average current mode control CCM algorithm, the NCP1651 can help provide excellent power factor while limiting the peak primary current. Also, the fixed frequency operation eases the input filter design. The NCP1651 uses a proprietary multiplier design that allows for much more accurate operation than with conventional analog multipliers. Features http://onsemi.com MARKING DIAGRAM SO-16 D SUFFIX CASE 751B 16 1 TBD A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS OUT 1 GND 2 CT 3 RAMP COMP 4 IS+ 5 Iavg- fltr 6 Iavg 7 FB/SD 8 (Top View) 16 STARTUP 15 NC 14 NC 13 VCC 12 Vref 11 AC COMP 10 AC REF 9 AC INPUT * * * * * * * * * * Fixed Frequency Operation Average Current Mode PWM Internal High Voltage Start-Up Circuit Continuous or Discontinuous Mode Operation High Accuracy Multiplier Overtemperature Shutdown External Shutdown Undervoltage Lockout Low Cost/Parts Count Solution Ramp Compensation Does Not Affect Oscillator Accuracy ORDERING INFORMATION Device NCP1651D NCP1651DR2 Package SO-16 SO-16 Shipping 48 Units/Rail 2500/Tape & Reel Typical Applications * High Current Battery Chargers * Front Ends for Distributed Power Systems This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 2003 1 April, 2003 - Rev. 2 Publication Order Number: NCP1651/D NCP1651 PIN FUNCTION DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 Function Output Ground CT Ramp Compensation IS+ Iavg- fltr Iavg Feedback/ Shutdown AC Input AC Reference AC Compensation Description Drive output for power FET or IGBT. Capable of driving small devices, or can be connected to an external driver for larger transistors. Ground reference for the circuit. Timing capacitor for the internal oscillator. This capacitor adjusts the oscillator frequency. This pin biases the ramp compensation circuit, to adjust the amount of compensation that is added to the current signal for stability purposes. Positive current sense input. Designed to connect to the positive side of the current shunt. A capacitor connected to this pin filters the high frequency component from the instantaneous current waveform, to create a waveform that resembles the average line current. An external resistor with a low temperature coefficient is connected from this terminal to ground, to set and stabilize the gain of the Current Sense Amplifier output that drives the ac error amplifier. The error signal from the error amplifier circuit is fed via an optocoupleer or other isolation circuit, to this pin. A shutdown circuit is also connected to this pin which will put the unit into a low power shutdown mode if this voltage is reduced to less than 0.6 volts. The rectified input ac haversine wave is connected to this pin. This information is used for the reference comparator and the average current compensation circuit. A capacitor is connected to this pin to filter the modulated output of the reference multiplier. Provides pole for the ac Reference Amplifier. This amplifier compares the sum of the ac input voltage and the low frequency component of the input current to the reference signal. The response must be slow enough to filter out most of the high frequency content of the current signal that is injected from the current sense amplifier, but fast enough to cause minimal distortion to the line frequency information. 6.5 volt regulated reference output. Provides power to the device. This pin is monitored for undervoltage and the unit will not operate if the VCC voltage is not within the UVLO range. Initial power is supplied to this pin via the high voltage start-up network. This pin is not available due to spacing considerations of the start-up pin. This pin is not available due to spacing considerations of the start-up pin. This pin connects to the rectified input signal and provides current to the internal bias circuitry for the start-up period of operation. 9 10 11 12 13 Vref VCC 14 15 16 No Connection No Connection Start-up NOTE: Pins 14 and 15 have not been used for clearance considerations due to the potential voltages present on pin 16. In order to maintain proper spacing between the high voltage and low voltage pins, traces should not be placed on the circuit board between pins 16 and 13. http://onsemi.com 2 NCP1651 MAXIMUM RATINGS (Maximum ratings are those that, if exceeded, may cause damage to the device. Electrical Characteristics are not guaranteed over this range.) Rating Power Supply Voltage (Operating) Output (Pin 1) Current Sense Amplifier Input (Pin 5) FB/SD Input (Pin 8) CT Input (Pin 3) Line Voltage All Other Pins Thermal Resistance, Junction-to-Air 0.1 in2 Copper 0.5 in2 Copper Thermal Resistance, Junction-to-Lead Maximum Power Dissipation @ TA = 25C Operating Temperature Range Non-operating Temperature Range qJA 130 110 qJL Pmax Tj Tj 50 0.77 -40 to 125 -55 to 150 C/W W C C Symbol VCC V(IS+) VFB/SD VCT Vstartup Value -0.3 to 18 -0.3 to 1.0 -0.3 to 11 -0.3 to 4.5 -0.3 to 500 -0.3 to 6.5 Unit V V V V V V C/W 1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. A. This device series contains ESD protection and exceeds the following tests: Pins 1-6: Human Body Model 2000 V per MIL-STD-883, Method 3015. Pins 1-6: Machine Model Method 200 V. Pin 8 is the HV start-up to the device and is rated to the maximum rating of the part, or 500 V. http://onsemi.com 3 NCP1651 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C12 = 0.1 mF, Tj = 25C for typical values. For min/max values Tj is the applicable junction temperature.) Characteristic OSCILLATOR Frequency Tj = -40C to +125C Frequency Range (Note 2) Max Duty Cycle Ramp Peak (Note 2) Ramp Valley (Note 2) Ramp Compensation Peak Voltage (Pin 4) (Note 2) Ramp Compensation Current (Pin 4) (Note 2) AC ERROR AMPLIFIER (Vcomp = 2.0 V) Input Offset Voltage Transconductance Output Source Output Sink CURRENT AMPLIFIER Input Bias Current (Pin 5) Input Offset Voltage (Vcomp = 2.0) Tj = -40C to +85C Tj = -40C to +125C Current Limit Threshold Output Gain (150 mA/0.150 V) (Voltage Loop Outputs) Output Gain (150 mA/0.150 V) (AC E/A Output) (R10 = 15 kW) Leading Edge Blanking Pulse (Note 2) Bandwidth (Note 2) PWM Output Voltage Gain (k = VPWM+ / (Vsense+ - Vsense- )) (Vpin 3 = Vpin 13 = 0) Current Limit Voltage Gain (k = Vace/a- / (Vsense+ - Vsense- )) (Vpin59 = 0) (R7 = 15 k) AVERAGE CURRENT COMPENSATION AMPLIFIER Voltage Gain REFERENCE MULTIPLIER Dynamic Input Voltage Range Ac Input (p-input) (Note 2) Offset Voltage (a-input) Multiplier Gain k+ (Note 2) AC INPUT (Pin 5) Input Bias Current (Total bias current for reference multiplier and current compensation amplifier) (Note 2) 2. Verified by design. IINbias 0.01 mA Vmult out (VAC Vramp pk) (VLOOPcomp * Voffset) Vmax k 7.5 3.50 1.0 V Av 0.75 V/V Ibias VIO ILIMthr tLEB Av Av 40 0 0 0.715 4.0 8.0 60 3.0 3.0 1000 1000 200 1.5 5.0 10 80 10 20 0.79 6.0 12 mA mV V umho umho ns MHz V/V V/V VIO gm IOsource IOsink 75 25 -25 20 100 70 -70 150 mV umho mA mA Fosc dmax VRpeak VRvalley 90 25 0.95 100 4.0 0.100 4.0 150 110 250 kHz kHz V V V mA Symbol Min Typ Max Unit http://onsemi.com 4 NCP1651 ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C12 = 0.1 mF, Tj = 25C for typical values. For min/max values Tj is the applicable junction temperature.) Characteristic DRIVE OUTPUT Source Resistance (1.0 Volt Drop) Sink Resistance (1.0 Volt Drop) Rise Time (CL = 1.0 nF) Fall Time (CL = 1.0 nF) Output Voltage in UVLO Condition (Drive out = 100 mA in, 1 nF load) VOLTAGE REFERENCE Buffered Output (Iload = 0 mA, VCC = 12 VDC, Temperature) Load Regulation (Buffered Output, Io = 0 to 10 mA, VCC > 10 V) FB/SD PIN Opto Current Source (Unit Operational, VFB = 0.5 V) Opto Current Source (Shutdown, VFB = 0.1 V) Input Voltage for 0 Duty Cycle (Note 3) Input Voltage for 95% Duty Cycle (Note 3) Open Circuit Voltage (Device Operational) (Note 3) Clamp Voltage (Device in Shutdown Mode) (Note 3) Shutdown Start Up Threshold (Pin 8) (Vout Increasing) Shutdown Hysteresis (Pin 8) STARTUP/UVLO UVLO Startup Threshold (VCC Increasing) UVLO Hysteresis (Shutdown Voltage = VSU - VH) Overtemperature Trip Point (Note 3) Overtemperature Hysteresis (Note 3) HIGH VOLTAGE START-UP (Pin 16 = 50 V) Start-up Current (out of pin 13) (VCC = UVLO - 0.2 V) Start-up Current (out of pin 13) (VCC = 0 V) Min. Start-up Voltage (pin 16, pin 13 current = 1 mA) Line Pin Leakage (pin 16, Start-up Circuit Inhibited) (VDS = 400 V, TA = +25C) TA = +125C TOTAL DEVICE Operational Bias Current (CL(Driver) = 1.0 nF, fosc = 100 kHz) Bias Current in Undervoltage Mode 3. Verified by design. IBIAS IBshutdown 4.0 0.75 5.0 1.2 mA mA VSU Ileak 25 15 40 80 ISU 3.0 5.0 5.5 8.5 17 8.0 12 20 mA mA V mA VSU VH TSD 10 0.8 140 10.75 1.0 160 30 11.5 1.2 180 V V C C VrefOUT DVrefOUT VOC VCL VSD VH 0.8 15 1.5 0.9 0.40 30 1.1 20 1.5 0.60 75 1.4 25 4.0 12 1.6 0.70 130 mA mA mV V V V mV VrefOUT DVrefOUT 6.24 0 6.50 6.76 40 V mV Rsource Rsink tr tf VO(UV) 8.0 8.0 50 50 1.0 15 15 10 W W ns ns mV Symbol Min Typ Max Unit http://onsemi.com 5 NCP1651 16 6.5 V REFERENCE REGULATOR STARTUP 13 VCC 4V 6.5 V Vref 12 20 mA 3.8 k FB/SD 8 0.50 V V-I CONVERTER OVERTEMPERATURE SENSOR + - UVLO SHUTDOWN R /8 COUNTER Q Clk A REFERENCE MULTIPLIER P 0.75 Vline + k Iin = Vref + - AC ERROR AMP AC REFERENCE BUFFER V-I 4V - + 16 k PWM R SET DOMINANT DRIVER AC INPUT 9 AC REF 10 S Q 25 k 4.5 V AC COMP 11 20 k + - 60 k AVERAGE CURRENT COMPENSATION GND 2 OSCILLATOR RAMP COMPENSATION + CURRENT SENSE AMPLIFIER LEB OUT 1 IS+ 5 RAMP COMP 4 3 CT Iavg 7 6 Iavg- fltr Figure 1. Block Diagram http://onsemi.com 6 NCP1651 DRIVE LATCH Q AC Error Amp + Ramp Comp + Inductor Current 4V PWM GND FB/SD 0.5 V GND OSCILLATOR RAMP OSCILLATOR BLANKING PULSE Figure 2. Switching Timing Diagram 7 7 VCC 10.8 V 9.8 V 8 1 2 3 7 8 7 7 7 8 STARTUP OFF ENABLE ON OUTPUT MAX CURRENT 0 FB/SD 0.5 V 0 SHUTDOWN START-UP CURRENT LIMIT SHUTDOWN Figure 3. Divide-by-Eight Counter Timing Diagram http://onsemi.com 7 NCP1651 Typical Performance Characteristics (Test circuits are located in the document TND308/D) 5 12 10 PIN 6 Vout (V) 3 PIN 7 Vpin 8 (V) 0 100 200 300 400 500 8 6 4 1 0 IS+ (mV) 2 0 0 200 400 600 800 Isink (mA) 1000 1200 1400 1600 4 2 Figure 4. Current Sense Amplifier Gain Figure 5. FB/SD V-I Characteristics 0.9 0.8 0.7 CURRENT (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 VCC (V) 8 10 12 -40 C 0C 25C 80C 125C BIAS CURRENT (mA) 5.0 VCC = 14 V 4.5 4.0 3.5 3.0 2.5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) Figure 6. Bias Current in Shutdown Mode Figure 7. Bias Current in Operating Mode 9 STARTUP CURRENT, PIN 16 (mA) 8 7 6 125C 5 80C 4 3 2 1 0 1 10 100 1000 STARTUP PIN VOLTAGE (V) LEAKAGE CURRENT, PIN 16 (mA) 25C -40 C 0C 39 34 29 24 19 14 9.0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) Figure 8. Startup Current versus High Voltage Figure 9. Startup Leakage versus Temperature http://onsemi.com 8 NCP1651 Typical Performance Characteristics (Test circuits are located in the document TND308/D) 11.2 TURN-ON 10.8 THRESHOLD (V) CLAMP VOLTAGE, PIN 8 (V) 125 1.5 1.0 10.5 10.2 TURN-OFF 9.8 9.5 -50 0.5 0 -25 0 25 50 75 100 0 2 4 6 VCC (V) 8 10 12 TEMPERATURE (C) Figure 10. UVLO versus Temperature Figure 11. FB/SD Clamp Voltage versus VCC 5 2.5 V 4.5 4 3.5 AC REF (V) 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 AC INPUT (V) 1.6 V 1.8 V 2.0 V FB/SD = 3.0 V 1000 VCC, CAPACITANCE (mF) 5 100 10 1 1 10 100 CHARGE TIME (ms) 1000 10,000 Figure 12. Reference Multiplier Gain Figure 13. VCC Cap Charge Time 100 k 4.40 4.35 4.30 RAMP PEAK NOTE: Ramp Valley Voltage is Zero for All Frequencies 10 k CT (pF) 4.25 4.20 4.15 4.10 4.05 4.00 1000 100 1 10 100 1000 FREQUENCY (kHz) 3.95 0 50 100 150 200 250 300 FREQUENCY (kHz) Figure 14. CT versus Frequency Figure 15. Ramp Peak versus Frequency http://onsemi.com 9 NCP1651 Typical Performance Characteristics (Test circuits are located in the document TND308/D) 99 98 97 96 95 94 93 0 50 100 150 200 250 300 FREQUENCY (kHz) 100 0 50 100 150 200 250 300 350 10% TO 90% DRIVE RISE AND FALL TIMES CAPACITANCE 10,000 FALL TIME RISE TIME MAXIMUM DUTY CYCLE 1000 Figure 16. Maximum Duty Cycle versus Frequency 110 Figure 17. Capacitance versus 10% to 90% Drive Rise and Fall Times FREQUENCY (kHz) Vref 50 mV/div 105 10 mA Vref Load 0 mA 100 95 90 -50 2.0 ms/div -25 0 25 50 75 100 125 150 TEMPERATURE (C) Figure 18. Transient Response for 6.5 Volt Reference Figure 19. Frequency versus Temperature http://onsemi.com 10 NCP1651 Typical Performance Characteristics (Test circuits are located in the document TND308/D) 4.12 PEAK RAMP VOLTAGE (V) NOTE: Valley Voltage is Zero 4.10 Vref (V) 6.50 -40 C 6.48 6.52 25C 4.08 4.06 6.46 125C 4.04 -50 6.44 -25 0 25 50 75 100 125 0 2 4 6 8 10 TEMPERATURE (C) Vref LOAD (mA) Figure 20. Peak Ramp Voltage versus Temperature Figure 21. Vref Load Regulation 1 0.8 NO LOAD Vref (V) 0.6 10 kW 0.4 3.3 kW 0.2 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 22. Vref in Shutdown Condition http://onsemi.com 11 NCP1651 6.5 V 3.8 k FB/SD 9 SHUT DOWN 470 V-I CONVERTER 5 AC INPUT A REFERENCE MULTIPLIER (Allows external converters to be synchronized to the switching frequency of this unit.) Figure 23. External Shutdown Circuit Vref 12 BAS16LT1 33 k AC COMP MMBT2907AL 11 R11 0.33 mF C11 NCP1651 Figure 24. Soft Start Circuit http://onsemi.com 12 NCP1651 THEORY OF OPERATION Introduction Optimizing the power factor of units operating off of ac lines is becoming more and more important. There are a number of reasons for this. There are a growing number of government regulations requiring PFC (Power Factor Correction). Many of these are originating in Europe. Regulations such as IEC1000-3-2 are forcing equipment to utilize input stages with topologies other than a simple off-line front end which contains a bridge rectifier and capacitor. There are also system requirements that dictate the use of PFC. In order to obtain the maximum power from an existing circuit in a building, the power factor is very critical. The real power available from such a circuit is: Preal + Vrms Irms PF reactive loads such as motors which are inductive, or electroluminescent lighting which is highly capacitive. In such a case the power factor is relatively simple to analyze, and is determined by the phase shift. PF + cos Q A typical off-line converter will have a power factor of 0.5 to 0.6, which means that for a given circuit breaker rating only 50% to 60% of the maximum power is available. If the power factor is increased to unity, the maximum available power can be obtained. There is a similar situation in aircraft systems, where a limited supply of power is available from the on-board generators. Increasing the power factor will increase the load on the aircraft without the need for a larger generator. V v, i t I OFF-LINE CONVERTER V I v, i t PFC CONVERTER Figure 25. Voltage and Current Waveforms Unity power factor is defined as the current waveform being in phase with the voltage, and undistorted. Therefore, there are two causes of power factor degradation - phase shift and distortion. Phase shift is normally caused by Where Q is the phase angle between the voltage and the current. Reduced power factor due to distortion is more complicated to analyze and is normally measured with ac analyzers, although most circuit simulation programs can also calculate power factor. One of the major causes of distortion is rectification of the line into a capacitive filter. This causes current spikes that do not follow the input voltage waveform. An example of this type of waveform is shown in the upper diagram in Figure 25. A power converter with PFC forces the current to follow the input waveform. This reduces the peak current, the rms current and eliminates any phase shift. In most modern PFC circuits, to lower the input current harmonics, and improve the input power factor, designers have historically used a boost topology. The boost topology can operate in the Continuous (CCM), Discontinuous (DCM), or Critical Conduction Mode. Most PFC applications using the boost topology are designed to use the universal input ac power 85-265 Vac, 50 or 60 Hz, and provide a regulated dc bus (typically 400 Vdc). In most applications, the load can not operate off the high voltage dc bus, so a dc-dc converter is used to provide isolation between the ac source and load, and provide a low voltage output. The advantages to this system configuration are, lowTHD, a power factor close to unity, excellent voltage regulation, and transient response on the isolated dc output. The major disadvantage of the boost topology is that two power stages are required which lowers the systems efficiency, increases components count, cost, and increases the size of the power supply. ON Semicondutor's NCP1651 offers a unique alternative for Power Factor Correction designs, where the NCP1651 has been designed to control a PFC circuit operating in a flyback topology. There are several major advantages to using the flyback topology. First, the user can create a low voltage isolated secondary output, with a single power stage, and still achieve a low input current distortion, and a power factor close to unity. A second advantage, compared to the boost topology with a dc-dc convertr, is a lower component count which reduces the size and the cost of the power supply. The NCP1651 can operate in either the Continuous or Discontinuous mode of operation, the following analysis will help to highlight the advantages of Continuous versus Discontinuous mode of operation. If we look at a single application and compare the results. PO = 90 watts Vin = 85-265 Vrms (analyzed at 85 Vrms input) http://onsemi.com 13 NCP1651 Efficiency = 80% Pin = 108 W VO = 48 Vdc Freq = 100 kHz Transformer turns ration N = 4 Continuous Mode (CCM) To force the inductor current to be continuous over the majority of the input voltage range (85-265 Vac), LP needs to be at least 1 mH. Figure 26 shows the typical current through the windings of the flyback transformer. During switch on period, this current flows in the primary and during the switch off time it flows in the secondary. IPK Iavg 250 200 (mA) TIME 150 100 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (MHz) Continuous Conduction Mode A second result of running in DCM can be higher input current distortion, EMI, and a lower Power Factor, in comparison to CCM. While the higher peak current can be filtered to produce the same performance result, it will require a larger filter. A simple Fast Fourier Transform (FFT) was run in Spice to provide a comparison between the harmonic current levels for CCM and DCM. The harmonic current levels will affect the size of the input EMI filter which in some applications are required to meet the levels of C.I.S.P.R. In the SPICE FFT model we did not add any front end filtering so the result of the analysis could be compared directly. 300 Figure 26. The peak current is: IPK = Iavg + ((1.414 Vin sin Q ton 2)/LP) where Iavg = 1.414 Pin/Vin sin Q Ton = T/((NS/NP 1.414 Vin sin Q /VO) +1) Ton = 6.19 ms IPK = (1.414 113)/85 sin Q + (1.414 85 6.15 ms 2) /1 mH = 3.35 A Discontinuous Mode (DCM) In the discontinuous mode of operation, the inductor curent falls to zero prior to the end of the switching period as shown in Figure 27. IPK Figure 28. Continuous Conduction Mode At the 100 kHz switching frequency, the rms value from the FFT is 260 mA, and the 2nd harmonic (200 kHz) is 55 mA rms. 2.8 2.4 2.0 1.6 Iavg (A) 1.2 0.8 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (MHz) TIME Figure 27. To ensure DCM, LP needs to be reduced to approximately 100 mH. IPK = (Vin sin Q 1.414 ton)/LP IPK = 1.414 85 sin 90 5.18 ms/100 mH = 6.23 A The results show that the peak current for a flyback converter operating in the Continuous Conduction Mode is one half the peak current of a flyback converter operating in the Discontinuous Conduction Mode. Figure 29. Discontinuous Conduction Mode At 100 kHz the rms value from the FFT are 2.8 A, and the 2nd harmonic (200 kHz) is 500 mA rms. http://onsemi.com 14 NCP1651 Results It is clear from the result of our analysis that a flyback PFC converter operating in CCM has half the peak current and one tenth the fundamental (100 kHz) harmonic current compared to a flyback PFC converter operating in DCM. The results are lower conduction losses in the MOSFET, and secondary rectifying diode, and a smaller input EMI filter if the designer needs to meet the requirements C.I.S.P.R. conducted emission levels. On the down side to CCM operation, the flyback transformer will be larger because of the required higher primary inductance. The advantages to operating in DCM include lower switching losses because the current falls to zero prior to the next switching cycle, and smaller transformer size. It will ultimately be up to the designer to perform a trade-of f study to determine which topology, Boost versus Flyback, Continuous versus Discontinuous Mode of operation will meet all the system performance requirements. But the recent introduction of the NCP1651 allows the system designer one additional option. For an average current mode flyback topology based PFC converter, determining the transformer parameters (primary inductance and turns ratio) involves several trade-offs. These include peak-to-average current ratio (higher inductance or turns ratio result in lower peak current), switching losses (higher turns ratio leads to higher peak voltage and higher switching losses), CCM vs. DCM operation (lower values of turns ratio or higher values of inductance extend the CCM range) and range of duty cycles over the operational line and load range. ON Semiconductor has designed an Excel-based spreadsheet to help design with the NCP1651 and balance these trade-offs. The design aid is downloadable free-of-charge from our web-site (www.onsemi.com). The ideal solution depends on the specific application requirements and the relative priority between factors such as THD performance, cost, size and efficiency. The design aid allows the designer to consider different scenarios and settle on the best solution foe a given application. Following guidelines will help in settling towards the most feasible solution. 1. Turns Ratio Limitations: While higher turns ratio can limit the reflected primary voltage and current, it is constrained by the inherent limitations of the flyback topology. A turns ratio of higher than 20:1 will result in very high leakage inductance and lead to high leakage spikes on the primary switch. Thus, practical application of this approach is restricted to output voltages 12 V and above. 2. CCM Operation: The NCP1651 is designed to operate in both CCM and DCM modes. However, the CCM operationresults in much better THD than the DCM operation. Thus, it is recommended that the circuit be designed to operate in CCM at the specified test condition for harmonics compliance (typically at 230 V, full load). Please keep in mind that at or near zero crossing (<10 deg angle), it is neither necessary nor feasible to maintain CCM operation. 3. Following key governing equations have been incorporated in the design aid: PFC Operation The basic PWM function of the NCP1651 is controlled by a small block of circuitry, which comprises the DC regulation loop and the PFC circuit. These components are shown in Figure 30. There are three inputs to this loop. They are the rectified input ac haversine, the instantaneous input current and the error signal at the FB/SD pin. The input current is forced to maintain a near unity power factor due to the control of the ac error amplifier. This amplifier uses information from the ac input voltage and the ac input current to control the power switch in a manner that gives good DC regulation as well as excellent power factor. The reference multiplier sets a reference level for the input haversine waveform. One of its inputs is connected to a scaled down haversine, and the other receives the error signal which has been converted to a current. The error signal adjusts the level of the haversine on the multiplier's output without distorting it. To accomplish this, it is necessary for the bandwidth of the DC error amp to be less than twice the lowest line frequency. Typically it is set at a factor of ten less than the rectified frequency (e.g. for a 60 Hz input, the bandwidth would be 12 Hz). http://onsemi.com 15 Rectified Line Figure 30. Simplified Block Diagram of Basic PFC Control Circuit D5 6.5 V Cout 20 mA 3.8 k FB/SD 8 680 4V - + PWM Verror(ac) 2 V-I CONVERTER REFERENCE MULTIPLIER Vref AC ERROR AMP + - .75 Vline + k Iin = Vref Verror(ac) V-I AC REFERENCE BUFFER CURRENT SENSE AMPLIFIER AVERAGE CURRENT COMPENSATION 10 REF FILTER PWM Logic DRIVER DRIVE 1 RDC1 http://onsemi.com RDC2 NCP1651 16 + IS+ 5 AC INPUT 9 Vline + - .75 NCP1651 The key to understanding how the input current is shaped into a high quality sine wave is the operation of the ac error amplifier. The inputs of an operational amplifier operating in its linear range, must be equal. There are several secondary effects, that create small differences between the inverting and non-inverting inputs, but for the purpose of this analysis they can be considered to be equal. The haversine output of the reference multiplier is fed into the non-inverting input of the ac error amplifier. The inverting input to the ac error amplifier receives a signal that is comprised of the input haversine (which is not modified by the reference multiplier), and summed with the filtered input current. Since the two inputs to this amplifier will be at the same potential, the complex signal at the non-inverting input will have the same waveshape as the ac reference signal. The ac reference signal (Vref) is a haversine, and the ac input signal (Vline) is also a haversine, therefore, the ac current signal (Iin), must also be a haversine. This relationship gives the formula: Vref + .75 @ Vref ) (k Iin) Verror(ac) Verror(ac) AC Input Vref Vline OSC k Iin Vref .75 Vline + k Iin 4 V ref Verror(ac) GND 4 V ref The Iin signal has a wide bandwidth, and its instantaneous value will not follow the low frequency haversine exactly, however, the output of the ac error amplifier has a low frequency pole that allows the average value of the .75 Vline + (k x Iin) to follow Vref. Since the ac error amplifier is a transconductance amplifier, it is followed by an inverting unity gain buffer stage with a low impedance output so that the signal can be summed with the instantaneous input switching current (Iin). The output of the buffer is still Verror(ac). GND Figure 31. Typical Signals for PFC Circuit The difference between Verror(ac) and the 4.0 volt reference, sets the window that the instantaneous current will modulate in, to determine when to turn the power switch off. The switch is turned on by the oscillator, which makes this a fixed frequency controller. Under normal operation, the switch will remain on until the instantaneous value of Verror(ac) reaches the 4.0 volt reference level, at which time the switch will turn off. Since the input current has a fundamental frequency that is twice that of the line, the output filter must have poles lower than the input current to create a reasonable DC waveform. The DC output voltage is compared to a reference voltage by a secondary side error amplifier, and the error signal out of the secondary side amplifier is fed back into the Feedback input through an optocoupler. http://onsemi.com 17 NCP1651 OPERATING DESCRIPTION DC Reference and Buffer The internal DC reference is a precision bandgap design with a nominal output voltage of 4.0 volts. It is temperature compensated, and trimmed for a "1% tolerance of its nominal voltage, with an overall tolerance of "2%. To assure maximum stability, this is only used as a reference so there is minimal loading on this source. The DC reference is fed into a buffer with a gain of 1.625 which creates a 6.5 volt supply. This is used as an internal voltage to power many of the blocks inside of the NCP1651 and is also available for external use. The 6.5 volt reference is designed to be terminated with at 0.1 mF capacitor for stability reasons. There is no buffer between the internal and external 6.5 volt supply, so care should be used when connecting external loads. A short or overload on this voltage output will inhibit the operation of the chip. Undervoltage Lockout An Undervoltage Lockout circuit (UVLO) is provided to assure that the unit does not exhibit undesirable behavior at low VCC levels. It also reduces power consumption to a level that allows rapid charging of the VCC cap. When the VCC cap is initially charging, the UVLO will hold the unit off, and in a low bias current mode until the VCC voltage reaches a nominal 10.8 volt level. At this point the unit will begin operation, and the UVLO will no longer be active. If the VCC voltage falls to a level that is 1.0 volts below the turn-on point, the UVLO circuit will again become active. When in the active (shutdown) state, the UVLO circuit removes power from all internal circuitry by shutting off the 6.5 volt supply. The 4.0 volt reference remains active, and the UVLO and Shutdown comparators are also active. Multiplier The NCP1651 uses a new proprietary concept for its Reference multiplier. This innovative design allows greatly improved accuracy compared to a conventional linear analog multiplier. The multiplier uses a PWM switching circuit to create a scalable output signal, with a very well defined gain. One input (A) to the multiplier is a voltage-to-current (V-I) converter. By converting the input voltage into a current, an overall multiplier gain can be accomplished. In addition, there will be no error in the output signal due to the series rectifier. The other signal (Input P) is input into the PWM comparator. This selects a pulse width for the comparator output. The current signal from the V-I converter is factored by the duty cycle of the PWM comparator, and then filtered by the RC network on the output. This network creates a low pass filter, and removes the high frequency content from the original waveform. INPUT A V to I CONVERTER INPUT P RAMP + - Inverting Input OUTPUT NI Input Figure 32. Simplified Multiplier Schematic The multiplier ramp is generated by the internal oscillator, and is the same signal as is used in the PWM. It will therefore have the same frequency as the power stage. It is not necessary for Input P (into the PWM comparator) to be a DC signal, low frequency ac signals (relative to the ramp frequency) work well also. The gain of the multiplier is determined by the current-to-voltage ratio of the V-I converter, the load resistor of the output filter and the peak and valley points of the sawtooth ramp. When the P input signal is at the peak of the ramp waveform, the comparator will allow the A input signal to pass without chopping it at all. This gives an output voltage of the A current multiplied by the output filter resistance. When the P input signal is at the ramp valley voltage, the comparator is held low and no current is passed into the output filter. In between these two extremes, the duty cycle (and therefore, the output signal) is proportional to the level of the P input signal. The output filter is a parallel RC network. The pole for this network needs to be greater than twice the highest line frequency (120 Hz for a 60 Hz line), and less than the switching frequency. A recommended starting point is a factor of 20 to 50 less than the switching frequency. The pole is calculated by the formula: fo + 2 p 1 R C So, for a 60 Hz line, and a 100 kHz switching frequency, a 2.0 kHz pole is a good starting point. This would be a factor of 50 below the switching frequency, and is still far enough above the 120 Hz rectified line frequency that it won't cause undesirable distortion. The reference multiplier contains an internal loading resistor, with a nominal value of 25 kWs. This is because the resistor that converts the A input voltage into a current is internal. Making both of these resistors internal, allows for http://onsemi.com 18 NCP1651 good accuracy and good temperature performance. Only a capacitor needs to added externally to properly compensate this multiplier. It is not recommended that an external parallel resistor be used at the "Ref Gain" pin, due to tolerance variations of the internal resistor. There is an offset in the compensation (A-input) to the reference multiplier. It is due to the V-I converter that feeds the input. The FB/SD signal is buffered by a voltage-to-current converter for the appropriate signal into the multiplier. The schematic for that converter follows. CURRENT MIRROR 3.8 k FB/SD 8 Vfb + - i1 6 X i1 imult Reference Multiplier 20 k Feedback/Shutdown The FB/SD pin is a multiple function pin. Its primary function is to port the error signal to the voltage-to-current converter that feeds the reference multiplier. The operating range for the feedback signal is from 1.0 to 4.0 volts. Below an input level of 1.5 volts, the PWM duty cycle is reduced to zero. At 4.0 volts the PWM is operating at its maximum duty cycle. The signal at this pin is also sensed by an internal comparator that will shutdown the unit if the voltage falls below 0.60 volts. Under normal operating conditions the signal at this input will be 1.5 volts or greater, and the shutdown circuit will be inactive. This circuit is designed such that a 680 Ohm resistor in series with the optocoupler will assure that the converter will go to zero duty cycle when the opto is on full, but will not go low enough to put the unit into its shutdown mode. The shutdown function can be used for multiple purposes including overvoltage, undervoltage or hot-swap control. An external transistor, open collector or open drain gate, connected to this pin can be used to pull it low, which will inhibit the operation of the chip, and change the operating state to a low power standby mode. An example of a shutdown circuit is shown in Figure 23. Ramp Compensation The Ramp Compensation pin allows the amount of ramp compensation to be adjusted for optimum performance. Ramp compensation is necessary in a current mode converter to stabilize the units operation when the duty cycle is greater than 50%. The amount of compensation required is dependant on several variables, including the boost inductor value, and the desires of the designer. The value should be based on the falling di/dt of the inductor current. For a boost inductor with a variable input voltage, this will vary over the ac input cycle, and with changes in the input line. A di/dt chart is included in the design spreadsheet that is available for the NCP1651. For optimum load transient performance, the ramp compensation should equal the falling di/dt at 100% duty cycle. For optimum line transient response, it should equal one half of the falling di/dt at 100% duty cycle. This pin is a buffered output of the oscillator, which provides a voltage equal to the ramp on the oscillator CT pin. A resistor from this pin to ground, programs a current that is transformed via a current mirror to the non-inverting input of the PWM comparator. The ramp voltage due to the inductor di/dt at the input to the PWM comparator is the current shunt voltage at pin 5 multiplied by 10, which is the gain of the current amplifier output that feeds the PWM. 1.5 V Figure 33. Multiplier V-I Converter The output current for this stage is: imult + 6 (Vfb * 1.5 V) 20 k Multiplier AC Ref 10 25 k 1k + - 4.5 V AC Error Amplifier Figure 34. Reference Multiplier Clamp Circuit There is a 1 k resistor between the AC Ref pin and the AC Error Amplifier for ESD protection. Due to this resistor, the voltage on pin 10 (AC Ref) will exceed 4.5 volts under some conditions, but the maximum voltage at the non-inverting AC Error Amplifier input will be clamped at 4.5 volts. http://onsemi.com 19 NCP1651 Current Sense Amp AC Ref Buffer + - i 1.6i 16 k PWM Comparator Oscillator + - 4 Ramp Compensation RRC Average Current Compensation The input signal to this amplifier is the input haversine. The amplifier is a unity gain amplifier, with a voltage divider on the output that attenuates the signal by a factor of 0.75. This scaled down haversine is summed with the low frequency current signal out of the current sense amplifier. The sum of these signals must equal the signal at the non-inverting input to the AC error amplifier, which is the output of the reference multiplier. Since there is a hard limit of 4.5 volts at the non-inverting input, the sum of the line voltage plus the current cannot exceed this level. A typical universal input design operates from 85 to 265 vac, which is a range of 3.1:1. The output of the Current Compensation amplifier will change by this amount to allow the maximum current to vary inversely to the line voltage. AC Error Amplifier The ac error amplifier is a transconductance amplifier. This amplifier forces a signal which is the sum of the current and input voltage to equal the ac reference signal from the reference multiplier. Transconductance amplifiers differ from voltage amplifiers in that the output is a high impedance with a controlled voltage-to-current gain. This amplifier has a nominal gain of 100 umhos (or 0.0001 amps/volt). This means that an input voltage differential of 10 mv would cause the output current to change by 1.0 mA. Its maximum output current is 30 mA. Current Sense Amplifier The current sense amplifier is a wide bandwidth amplifier with a differential input. It consists of a differential input stage, a high frequency current mirror (PWM output) and a low frequency current mirror (ac error amp output). CURRENT MIRROR CURRENT MIRROR LEB Figure 35. Ramp Compensation Circuit The current mirror is designed with a 1:1.6 current ratio. The ramp signal injected can be calculated by the following formula: Vramp + 1.6 Voscpk 16 k RRC + 102, 400 RRC (eq. 1) Where: Vramp = Peak injected current signal (4 V) RRC = Ramp compensation resistor (kW) Oscillator The oscillator generates the sawtooth ramp signal that sets the switching frequency, as well as sets the gain for the multipliers. Both the frequency and the peak-to-peak amplitude are important parameters. The oscillator uses a current source for charging the capacitor on the CT pin. The charge rate is approximately 200 mA and is trimmed to maintain an accurate, repeatable frequency. Discharge is accomplished by grounding the CT pin with a saturated transistor. A hysteretic comparator monitors that ramp signal and is used to switch between the current source and discharge transistor. While the cap is charging, the comparator has a reference voltage of 4.0 volts. When the ramp reaches that voltage, the comparator switches from the charging circuit to the discharge circuit, and its reference changes from 4.0 to X0.5 volts (overshoot and delays will allow the valley voltage to reach 0 volts). The relationship between the frequency and timing capacitor is: CT + 47, 000 f i1 i1 i1 i2 PWM i2 3k 3k 30 k + - AC Error Amp IS+ 5 6 Iavg fltr 7 Iavg Where CT is in pF and f is in kHz. It is important not to load the capacitor on this pin, since this could affect the accuracy of the frequency as well as that of the multipliers which use the ramp signal. Any use of this signal should incorporate a high impedence buffer. Due to the required accuracy of the peak and valley ramp voltages, the NCP1651 is not designed to be synchronized to the frequency of another oscillator. Figure 36. Current Sense Amplifier The input to the current sense amplifier is a common base configuration. The voltage developed across the current shunt is sensed at the Is+ input. The amplifier input is designed for positive going voltages only; the power stage should resemble the configuration of the application circuit in Figure 38. http://onsemi.com 20 NCP1651 Caution should be exercised when designing a filter between the shunt resistor and this input, due to the low impedance of this amplifier. Any series resistance due to a filter, will create an offset of: VOS + 50 mA Rexternal which will add a positive offset to the current signal. The effect of this is that the ac error amplifier will try to compensate for the average output current which appears never to go to zero, and cause additional zero crossing distortion. The voltage across the current shunt resistor is converted into a current (i1), which drives a current mirror. The output of the i1 current mirror is a high frequency signal that is a replica of the instantaneous current in the switch. The conversion of the current sense signal to current i1 is: i1 + Vis) 3 k The PWM output sends that information directly to the PWM input where it is added to the ac error amp signal and the ramp compensation signal. The Leading Edge Blanking circuit (LEB) interrupts the current signal to the PWM comparator for the first 200 ns of the switching pulse. This blanks out any spike that might occur at turn on, which could cause false triggering of the PWM comparator. The other output of the i1 mirror provides a voltage signal to a buffer amplifier. This signal is the result of i1 dropped across an internal 30 kW resistor, and filtered by a capacitor at pin 6. This signal, when properly filtered, will be the 2x line frequency haversine. The filter pole on pin 6 should be far enough below the switching frequency to remove most of the high frequency component, but high enough above the line frequency so as not to cause significant distortion to the input haversine waveform. For a 100 kHz switching frequency and a 60 Hz line frequency, a 10 kHz pole will normally work well. The capacitor at pin 6 can be calculated knowing the desired pole frequency by the equation: C6 + The NCP1651 uses a voltage mode Pulse Width Modulation scheme based on a fixed frequency oscillator. The oscillator outputs a ramp waveform as well as a pulse which is coincident with the falling edge of the ramp. The pulse is fed into the PWM latch and OR gate that follows. During the pulse, the latch is reset, and the output drive is in its low state. On the falling edge of the pulse, the output drive goes high and the power switch begins conduction. The instantaneous inductor current is summed with the ac error amplifier voltage and the ramp compensation signal to create a complex waveform that is compared to the 4.0 volt reference signal on the inverting input to the PWM comparator. When the signal at the non-inverting input to the PWM comparator exceeds 4.0 volts, the output of the PWM comparator changes to a high state which drives one of the Set inputs to the latch and turns the power switch off until the next oscillator cycle. The OR gate that follows the PWM is used to inhibit the drive signal to the power switch. In addition to the oscillator pulse, this gate receives a signal from the shutdown OR gate, which can inhibit operation due to an overtemperature condition, shutdown signal, or insufficient VCC. Driver The output driver can be used to directly drive a FET, for low and medium power applications, or a larger driver for high power applications. It is a complementary MOS, totem pole design, and is capable of sourcing and sinking over 1.5 amps, with typical rise and fall times of 50 ns with a 1.0 nF load. The totem pole output has been optimized to minimize cross conduction current during high speed operation. Additional internal circuitry has been added to keep the Driver in its low state whenever the Undervoltage Lockout is active. This characteristic eliminates the need for an external gate pull-down resistor. Shutdown Modes and Logic Overtemperature A temperature sensor and reference is provided to monitor the junction temperature of the chip. The chip will operate to a nominal temperature of 160C at which time the output of the temperature sensor will change to a low state. This will set the output of the shutdown NAND gate high, which in turn will set the output of the PWM OR gate high, and force the driver into a low state. There is a hysteresis of 30C on this circuit, which will allow the chip to cool down to 130C before resuming operation. While in the overtemperature shutdown mode, the start-up circuit will be operational and the VCC will cycle between 10.8 and 9.8 volts. Insufficient VCC If the level of the VCC voltage is not sufficient to maintain operation, the drive of the chip will be inhibited and the divide-by-eight timer will be invoked. This will normally occur when the output is overloaded. Under this condition, the divide-by-eight counter will count for 8 VCC cycles. At the end of the eighth cycle the driver Where: C6 = Pin 6 capacitance (nF) f = pole frequency (kHz) 1 2 p f30k or, for a 10 kHz pole, C6 would be 0.5 nF. The gain of the low frequency current buffer is set by the value of the resistor at pin 7. The value of R7 determines the scale factor between the peak current and the average current. The average current will be that of the primary waveform only, since the secondary current will not conduct across the shunt resistor. PWM Logic The PWM and logic circuits are comprised of a PWM comparator, an RS flip-flop (latch) and an OR gate. The latch is Set dominant which means that if both R and S are high the S signal will dominate and Q will be high, which will hold the power switch off. http://onsemi.com 21 NCP1651 will be enabled and the circuit will attempt to start. If the failure has been corrected, the output will come up and the circuit will resume normal operation. If not, another cycle will begin. The waveforms for overload timeout are shown in Figure 3. Shutdown The NCP1651 has a shutdown circuit that can be used to inhibit the operation of the chip by reducing the FB/SD pin voltage to less than 0.6 volts. When a shutdown signal is issued, the output of the shutdown comparator goes low. This immediately ceases the operation of the unit by OR'ing that signal to the output of the PWM logic, and holding the driver in its low state. The inverted output of the shutdown comparator is fed in to the reset pin of the divide-by-eight counter. The counter reset pin sets its count to seven. As long as the reset pin is low, the counter will remain at seven. When the shutdown signal is removed, the reset pin will go high, and the counter will continue to count to eight. The counter is triggered on the negative edge of the start-up enable signal. This means that a shutdown signal that is removed on the upward VCC slope will be in the 7 count for the remaining rise and fall of that VCC cycle and will change to 8 on the next cycle. This system assures that the unit will not be enabled until the VCC voltage has a full discharge cycle available, and it also insures that the unit will commence operation in less than two VCC cycles. A timing diagram of this mode of operation is shown in Figure 3. The count for the divide-by-eight counter is shown as 7, 7, 7, 8 which illustrates the operation of the reset function. If the shutdown signal is terminated before the VCC voltage reaches the lower UVLO limit (i.e. 9.8 volts), the unit will resume operation on the following VCC down slope, and if the shutdown signal is terminated on the VCC upward slope, the unit will resume operation on the second VCC down slope. AC Reference Buffer The ac reference buffer converts the voltage generated by the ac error amplifier to be converted into a current to be summed with the ramp compensation signal and the instantaneous current signal. CURRENT MIRROR 2.9 V AC ERROR AMP + - The buffer amplifier, converts the input voltage to a current by creating a current equal to the voltage difference between the ac error amplifier output and the 2.9 volt reference dropped across the 6.7 kW resistor. The bipolar transistor level shifts the voltage and maintains the proper current into the current mirror. The current mirror has a 1:1 ratio and delivers its output current to the PWM input. This current is summed with the currents of the ramp compensation signal and the instantaneous current signal to determine the turn-off point in the switching cycle. Start-Up Circuit The start-up circuit serves several functions. In addition to providing the initial charge on the VCC capacitor, it serves as a timer for the start-up, overcurrent, and shutdown modes of operation. Due to the nature of this circuit, this chip must be biased using the start-up circuit and an auxiliary winding on the power transformer. Attempting to operate this chip off of a fixed voltage supply will cause the chip to latch up in some modes of operation. A high voltage FET is biased as a current source to provide current for start- up power. On the application of input voltage, the high voltage start- up circuit is enabled and current is drawn from the rectified ac line to charge the VCC cap. When the voltage on the VCC cap reaches the turn on point for the UVLO circuit (10.8 volts typical), the start-up circuit is disabled, and the PWM circuit is enabled. With the NCP1651 enabled, the bias current increases from its standby level to the operational level. The divide-by-eight counter is preset to the count of 7, so that on start-up the chip will not be operational on the first cycle. The second VCC cycle will be number 8, and the chip will be allowed to start at this time. In the shutdown mode, the VCC cycle is held in the 7 count state until the shutdown signal is removed. This allows for a repeatable, fast restart. See Figure 3 for timing diagram. The unit will remain operational as long as the VCC voltage remains above the UVLO undervoltage trip point. If the VCC voltage is reduced to the undervoltage trip point, operation of the unit will be disabled, the start-up circuit will again be enabled, and will charge the VCC cap up to the turn on voltage level. At this point the start-up circuit will turn off and the unit will remain in the shutdown mode. This will continue for the next seven cycles. On the eighth cycle, the NPC1651 will again become operational. If the VCC voltage remains above the undervoltage trip point the unit will continue to operate, if not the unit will begin another divide-by-eight cycle. The purpose of the divide-by-eight counter is to reduce the power dissipation of the chip under overload conditions and allow it to recycle indefinitely without overheating the chip. It is critical that the output voltage reaches a level that allows the auxiliary voltage to remain above the UVLO turn- off level before the VCC cap has discharged to that level. If the bias voltage generated by the inductor winding fails to exceed the shutdown voltage before the capacitor reduces to the UVLO i1 i1 PWM, Ramp Comp Current Sense Amp AC Comp 3 16 k + - 6.7 k Unity Gain Amplifier Figure 37. AC Reference Buffer Schematic The buffer's transfer function is: iout + (2.9 V * Vac(ea)) 6.7 k http://onsemi.com 22 NCP1651 undervoltage turn- off level, the unit will shut down and go into a divide- by- eight cycle, and will never start. If this occurs, the VCC capacitor value should be increased. Soft-Start Circuit The ac error amplifier has been configured such that a low output level will cause the output duty cycle to go to zero. This will have the effect of soft-starting the unit at turn-on, since the output is coupled to ground through a capacitor. There will be an initial offset of the output voltage due to the output current and the resistor at pin 11. For example, if the output is saturated in the high state at turn on, it will source 50 mA. If pin 11 is terminated with a 2.2 kW resistor and a 0.01 F capacitor, the initial step will be: 50 mA 2.2 k + 0.11 volts and the rate of rise will be: 50 mA 0.01 mF + 5 mV ms or, 560 ms until the output is at 2.8 volts, which corresponds to full duty cycle. There is also a clamp on pin 8 that will keep the capacitance on that pin discharged to 1.5 volts so that the FB/SD signal will also slew up from a low power level to a high power level. When the unit is in standby mode, the clamp will be enabled. At the same time as the unit is enabled, the clamp will be disabled to allow the feedback signal to control the loop. An external soft-start circuit can be added, as shown in Figure 24, if additional time is desired. http://onsemi.com 23 D1 STARTUP 16 4V 12 Vref Cref 0.47 mF 6.5 V VCC 13 Vin 6.5 V 20 mA UVLO REFERENCE REGULATOR D2 Cin D3 D4 Rac1 3.8 k / 8 COUNTER SHUTDOWN FB/SD 0.6 V V-I CONVERTER OVERTEMPERATURE SENSOR AC REFERENCE BUFFER AC ERROR AMP V-I 4V L1 S PWM R Cout 453 SET DOMINANT DRIVER OUT RAMP COMPENSATION 20 k + OSCILLATOR Rshunt 5.23 k CURRENT SENSE AMPLIFIER LEB 5 1 IS+ 422 Q1 Q 9.31 k 8 NOTE: This is a theoretical design, and it is not implied that a circuit designed by this procedure will operate properly without normal troubleshooting and adjustments as are common with any power conversion circuit. ON Semiconductor provides a spread sheet that incorporates the relevant equations, and will calculate the bias components for a circuit using the schematic shown. 680 1 mF - + a REFERENCE MULTIPLIER p 0.75 Vline + k Iin = Vref 16 k 12 V AC INPUT 9 AC REF 25 k 4.5 V - + - + + - 4.7 k NCP1651 DESIGN GUIDELINES Figure 38. Typical Application Schematic http://onsemi.com + - 60 k AVERAGE CURRENT COMPENSATION 4 RAMP COMP R13 3 CT Ctiming Iavg R10 7 6 Iavg fltr C12 24 10 UNDERVOLTAGE COMPARATOR Rac2 AC COMP Cac C4 11 - + R3 ERROR AMPLIFIER MC3303 7.5 k C3 - + GND OVERVOLTAGE COMPARATOR 2 4.02 k 0.01 mF TL431 5.23 k Rtn 2 NCP1651 Basic Specifications The design of any power converter begins with a basic set of specifications. The following parameters should be known before you begin: Pomax (Maximum rated output power) Vrmsmin (Minimum operational line voltage) Vrmsmax (Maximum operational line voltage) fswitch (Nominal switching frequency) Vout (Nominal regulated output voltage) Most of these parameters will be dictated by system requirements. Transformer For an average current mode, fixed frequency PFC converter, there is no magic formula to determine the optimum value of the transformer's primary inductance. There are several trade-offs that should be considered. These include peak current vs. average current, switching losses vs. core losses and range of duty cycles over the operational line and load range. All of these are a function of inductance, line and load. These parameters determine when the converter is operating in the continuous conduction mode and when it is operating in the discontinuous conduction mode. If you are designing your own transformer, the ON Semiconductor spreadsheet (NCP1651_Design.xls) that is available as a design aid for this part can be of help. Enter various values of inductance as well as the turns ratio and observe the variation in duty cycle and peak current vs. average current. The transformer's duty cycle is an important parameter. There are two main limitations for the duty cycle. The first is the output voltage reflected back to the primary, which is scaled by the turns ratio. This means that with a 10:1 (pri:sec) turns ratio, and a 12 volt output, the power switch will see the input voltage plus 120 volts (10 x 12 volts) plus leakage inductance spike. This reflected voltage determines the maximum voltage rating of the power switch. The second, there are practical limits to the turns ratio. Given the flyback converter transfer function, continuous conduction mode, VO + Vin n (D 1 * D) Using the available spreadsheet, with the following parameters, a primary inductance of 330 mH and a turns ratio of 10:1 would be a good choice. Limits Pomax = 100 W Vinmax = 265 Vrms Vinmin = 85 Vrms VO = 12 V LP = 330 mH fswitch = 100 kHz Np/Ns = 10 6 PEAK CURRENT 5 CURRENT (A) 4 3 2 1 0 0 45 90 PHASE ANGLE () 135 180 PEDESTAL CURRENT Figure 39. Switching Current versus Phase Angle 100 100% = Discontinuous 50% = Continuous DUTY CYCLE (%) 75 50 MODE 25 DUTY CYCLE 0 0 45 90 DEGREES () 135 180 It is evident that there is a direct relationship between duty cycle and the turns ratio. In general, 10:1 is about the maximum, although some transformer manufacturers go as high as 12:1 or even 15:1. Turns ratios of 20:1 and above are not normally practical as they result in very high values of leakage inductance, which creates large spikes on the power switch. They also have a very large reflectdvoltage associated with them. The other option is to contact a transformer manufacturer such as Coiltronics (www.cooperet.com/) or Coilcraft (www.coilcraft.com/). These companies will design and manufacture transformers to your requirements. Figure 40. Continuous/Discontinuous and Duty Cycle If an auxiliary winding is desired to provide a bias supply, it should provide a minimum of 12.1 volts (to exceed the UVLO spec) and a maximum of 18 volts. The auxiliary winding should be connected such that it conducts when the power switch is off. Near the zero crossings of the line freqency, the voltage will have a peak voltage equal to the regulated output voltage divided by the turns ratio. The filter http://onsemi.com 25 NCP1651 cap on the VCC pin needs to be of sufficient size to hold the voltage up over between the zero crossings. Error Amplifier The error amplifier resides on the secondary side of the circuit, and therefore is not part of the chip. A minimal solution would include either a discrete amplifier and reference, or an integrated circuit that combines both, such as the TL431 series of regulators. Vout FB/SD Ropto Rdc1 Rfb Cfb 5.23 k V Vref2 Rdc2 - + 5.23 k 9.31 k Rout 12 V 3.6 k Ropto Cout 453 + - Undervoltage Capacitor 422 - + Error Amplifier - + MC3303 7.5 k Rbias Overvoltage Comparator 4.02 k 0.01 mF TL431 Error Amp Rtn Figure 42. Error Amp with Over/Undershoot Protection Figure 41. Error Amplifier Circuit This configuration for the error amplifier will result in a low cost regulator, however, due to the slow loop response of a PFC regulator it will not protect against overvoltage conditions (e.g. load removal) or droop when a transient load is added. The primary side circuit has been designed such that the PFC controller will operate at maximum duty cycle with the optocouple in a non-conducting state. This is necessary to allow the unit to bring up the output when the system is initially energized. At this time there is not output voltage available to drive the LED in the optocoupler. In the circuit of Figure 41, the amplifier and reference need to be rated at the maximum voltage that the output will experience, including transient conditions. Resistors Rdc1 and Rdc2 need to be chosen such that the voltage at V is equal to Vref2 when Vout is at its regulated voltage. Ropto is a current limiting resistor that protects the optocoupler from current transients due to output surges. This design also includes inherent compensation from transients. Since the bandwidth of the error amplifier is very low, its output can not respond rapidly to changes in the output voltage. A transient change in the output voltage will change the current through Ropto. Since the output of the error amplifier does not change immediately, if the output voltage increases, the voltage across Ropto will increase. This drives more current through the optocoupler, which in turn reduces the output of the converter. An alternate regulator is recommended, which is only slightly more expensive, and offers excellent protection from positive transients, and quick recovery from negative transients. The configuration shown in Figure 42, incorporates an error amplifier with slow loop response, plus overvoltage and undervoltage comparators. Under normal operation the outputs of the Undervoltage and Overvoltage Comparators are high. The Undervoltage Comparator provids drive for the optocoupler, while the Overvoltage Compartor reverse biases the diode on its output and is out of the loop. This circuit is designed with 8% trip points both above and below the regulation limit. If an overvoltage condition exists, the Overvoltage comparator will respond very quickly. When its output goes low, it will provide maximum drive to the optocoupler, which will shut off the output of the converter. If the output voltage drops 8% or more below its regulated level, the Undervoltage Comparator will go low. This will remove the drive from the optocoupler, which will allow the regulator to increase the duty cycle and return the output to its regulation range much faster than the error amplifier could. This configuration will work over a range of 5 to 30 volts, with the appropriate changes in Rout, Rbias and Ropto. Rout (kW) = (Vout - 4.753) / 0.7785 Rbias (kW) = (Vout - 4.4) Ropto (kW) = (Vout - 3) / 2 The value for Ropto will allow a maximum of 2 mA to drive the optocoupler. If additional current is needed, change the 2 in the denominator of that equation to the current (in mA) that is desired. http://onsemi.com 26 NCP1651 Ac Voltage Divider The voltage divider from the input rectifiers to ground is a simple but important calculation. For this calculation it is necessary to know the maximum line that the unit can operate at. The peak input voltage will be: Vinpeak = 1.414 x Vrmsmax The maximum voltage at the ac input (pin 5) is 3.75 volts (this is true for both multipliers). If the maximum line voltage is 265 Vac, the peak input voltage is: Vinpeak = 1.414 x 265 Vrms = 375 Vpk To keep the power dissipation reasonable for a 1/2 watt resistor (Rac1), it should dissipate no more than 1/4 watt. The power in this resistor is: PRac1 = (375 V - 3.75 V)2 / Rac1 = 0.25 watts so: Rac1 = 551 kW To minimize dissipation, use the next largest standard value, or 560 kW. Typically, two 1/4 resistors are used in series to handle the power. Then, Rac2 = 3.75 V / ((375 V - 3.75 V) / 560 k) = 5.6 kW Current Sense Resistor/Ramp Compensation The combination of the voltage developed across the current sense resistor and ramp compensation signal, will determine the peak instantaneous current that the power switch will be allowed to conduct before it is turned off. The vector sum of the three signals that combine to create the signal at the non-inverting input to the PWM comparator must add up to 4.0 volts in order to terminate the switch cycle. These signals are the error signal from the ac error amp, the ramp compensation signal, and the instantaneous current. For a worst case condition, the output of the ac error amp could be zero (current), which would require that the sum of the ramp compensation signal and current signal be 4.0 volts. This must be evaluated under full load and low line conditions. For proper ramp compensation, the ramp signal should match the falling di/dt (which has been converted to a dv/dt) of the inductor at 50% duty cycle. 50% duty cycle will occur when the input voltage is 50% of the output voltage. Both the falling di/dt and output voltage need to be reflected by the transformer turns ratio to the primary side. Thus the following equations for RS and RRC must be satisfied: di/dt primary = Vin/LP T/2 di/dt secondary = VO/LS T/2 NS LS + NP VO LP NP NS 2 di/dt primary = di/dt secondary Vin/LP T/2 = VO/LP NP/NS T/2 Vin/LP = VO/LP NP/NS Equation 2) For proper slope compensation, the relationship between RS and RRC is: di/dt (primary) T RS High Frequency Current Gain = VRcomp VO/LP T NP/NS RS 16 k/3 k = 102.4 k/RRC RS = (19,200/RRC T) (LP/VO) (NS/NP) Equation 3) ton = T/(NS/NP (2 VLL/VO)) + 1 For maximum output current, when the error amplifier is saturated in a low state, the ramp compensation signal plus the current signal must equal 4.0 volts (3.8 volts is used to avoid over driving the amplifier), which is the reference level for the PWM comparator. So: Equation 4) VrefPWM = VinST + VRcomp 3.8 V = IPK RS 16 k/3 k + 102.4 k/RRC ton/T RRC + 102.4 k ton (3.8 * 5.3 IPK RS) 3.8 ) 5.33 Ipk Combining equations 2 and 4 gives: RS + N P tonVO NS 0.1875 LP Where: RS is the current shunt resistor (Ohms) RRC is the ramp compensation resistor (Ohms) ton is the on time for the conditions given (ms) T is the period for the switching frequency (ms) LP is the primary inductance of the transformer (mH) Vout is the output voltage (VDC) Vrms is the rms line voltage at low line (Vrms) Pout is the output power at full load (watts) Iavg (T) is the avg current for one switching cycle (A) Ipk is the instantaneous peak primary side current (A) V(t) is the peak line voltage (volts) NP/NS is the transformer turns ratio (dimensionless) Current Scaling Resistor & Filter Capacitor R7 sets the gain of the averaged current signal out of the current sense amplifier which is fed into the ac error amplifier. R7 is used to scale the current to the appropriate level for protection purposes in the ac error amplifier circuit. R7 should be calculated to limit the maximum current signal at the input to the ac error amplifier to less than 4.5 volts at low line and full load. 4.5 volts is the clamp voltage at the output of the reference amplifier and limits the maximum averaged current that the unit can process. The equation for R7 is: R7 + 212 k @ RS @ Pin VinLL 4.5 * (0.75 @ ACratio @ VinLL @ 2 ) LP di/dt reflected to the primary: 2 N @T@ S 2 NP Simplifies to: VO/LP NP/NS T/2 http://onsemi.com 27 NCP1651 Where: Pin = rated input power (W) Where: RS = Shunt resistance (W) Where: VinLL = min. operating rms input voltage (W) Where: ACratio = ac attenuation factor at pin 9 This equation does not allow for tolerances, and it would be advisable to increase the input power to assure operation at maximum power over production tolerance variations. The current sense filter capacitor should be selected to set its pole about a factor of 10 below the switching frequency. C6 + 5.3 f To determine the values of R3 and C3, it is necessary to look at the two signals that reach the PWM inputs. The non-inverting input is a slow loop using the averaged current signal. It's gain is: AIf + 30 k @ 15 k @ (gm @ R11) @ 2.3 3k R7 Where: C6 = Pin 6 capacitance (nF) Where: f = pole frequency (kHz) so, for a 100 kHz switching frequency, a 10 kHz pole is desirable, and C6 would be 0.5 nF. Reference Multiplier The output of the reference multiplier is a pulse width modulated representation of the analog input. The multiplier is internally loaded with a resistor to ground which will set the DC gain. An external capacitor is required to filter the signal back into one that resembles the input haversine. The pole for this circuit should be greater than the line frequency and lower than the switching frequency. 1/15th of the switching frequency is a recommended starting value for a 60 Hz line frequency. The filter capacitor for pin 10 can be determined by the following equation: C10 + 1 + 6.366E- 6 2 3.14 25 k fpole fpole Where the first two terms are the gains in the current sense amplifier averaging circuit. The next term is the gain of the transconductance amplifier and the constant is the gain of the ac Reference Buffer. The high frequency path is that of the instantaneous current signal to the PWM non-inverting input. This gain is 16 k/3 k = 5.33, since the input signal is converted to a current through a 3 k resistor in the current sense amplifier, and then terminated by the 16 k resistor at the PWM input. For stability, the gain of the low frequency path must be less than the gain of the high frequency path. This can be written as: 345, 000 @ gm @ R11 R7 t 5.3 The suggested resistor and capacitor values are: R11 + R7 130,000 gm 1.59 fSW R11 and for a zero at 1/10th of the switching frequency C11 + Where: C10 = Pin 10 capacitance (F) Where: fpole = Ref gain pole freq (Hz) AC Error Amplifier The ac error amplifier is a transonductance amplifier that is terminated with a series RC impedance. This creates a pole-zero pair. Where: Where: Where: Where: R7 & R11 are in units of Ohms gm is in units of mhos C11 is in Farads fsw is in Hz http://onsemi.com 28 NCP1651 Loop Compensation Vline 6.5 V Rdc1 Ropto Vac Rac1 Np : Ns Vo Rac2 3.8 k Vfb FB/SD 8 Vref AC ERROR AMP Q1 4V C RL REFERENCE MULTIPLIER - + - + PWM OUT LOGIC 1 25 k 5 Rfb V Vref2 C.S. Amp Cfb IS+ RS Vea C8 ERROR AMP 0.022 mF C10 R7 Ref Fltr 10 Iavg 7 Iin - + Rdc2 DIVIDER Rdc2 V + Rdc1 ) Rdc2 Vo ERROR AMP fz + for f > fz: Av + Rfb Rdc1 for f < fz: Av + 1 2 p f Cfb Rdc1 1 2 p Cfb Rfb OPTO TRANSFER DVfb 3.8 k CTR + DVea Ropto REFERENCE SIGNAL DVref + 2.66 Vac DVfb Vline Rac2 Rac1 ) Rac2 MODULATOR AND OUTPUT STAGE DIin R7 + DVref RS 75, 000 Np DVout T *1 + h RL ton Ns DIin 1 2 p RL C Vac + fp + Figure 43. Voltage Regulation Loop Loop Model The model for the voltage loop has been broken down into six sections. The voltage divider, error amplifier, and opto Transfer are external to the chip, and the reference signal, modulator and output stage are internal. The modulator and output stage circuitry is greatly simplified based on the assumption that that poles and zeros in the current feedback loop are considerably greater than the bandwidth of the overall loop. This should be a good assumption, because a bandwidth in the kilohertz is necessary for a good current waveform, and the voltage error amplifier needs to have a bandwidth of less than the lowest line frequency that will be used. There are two poles in this circuit. The output filter has a pole that varies with the load. The pole on the voltage error amplifier will be determined by this analysis. Voltage Divider The voltage divider is located on the secondary side circuitry. It is a simple resistive divider that reduces the output voltage to the level required by the internal reference on the voltage error amplifier. If the amplifier circuit of Figure 42 is used, there are four resistors instead of 2. To determine the gain of this circuit, Rdc1 is the equivalent of the upper two resistors, 9.31 k and 453 Ohms respectively, and Rdc2 is the equivalent of the lower two resistors, 422 and 5.23 k respectively. Voltage Error Amplifier The voltage error amplifier is constrained by the two equations. When this amplifier is compensated with a pole-zero pair, there will be a unity gain pole which will be cancelled by the zero at frequency fz. The corresponding bode plot would be: 20 GAIN (dB) Unity Gain 0 AV fz -20 f, FREQUENCY Figure 44. Pole-zero Bode Plot The gain at frequencies greater than fz is determined by Rfb. Once Rfb is determined, the value of Cfb can be easily calculted using the formula for fz. http://onsemi.com 29 NCP1651 Optocoupler Transfer The optocoupler is used to allow for galvanic isolation for the error signal from the secondary to primary side circuits. The gain is based on the Current Transfer Ratio of the device. This can change over temperature and time, but will not result in a large change in dB. The recommended capacitor at pin 8 is .022 mF. If a larger capacitor is used, the pole may become low enough that it will have an effect on the gain phase plots near the unity gain crossover frequency. In this case and additional zero will be required in the error amplifier bias circuitry. Reference Signal The error signal is transmitted to the primary side circuit via. the optocoupler, is converted to a current by the V-I converter and is then used as an input to the reference multiplier. The gain of this block is dependent on the ac input voltage, because of the multiplier which requires two inputs for one output. Modultator and Output Stage The modulator receives an input from the reference multiplier and forces the current to follow the shape and amplitude. The is an internal loop within this section due to the current sense amplifier. Based on the assumptions listed in the introduction to this analysis, this is not analyzed separately. The equation for the gain is good for frequencies below the pole. There is a single pole due to the output filter. Since the NCP1651 is a current mode converter, the inductor is not part of the output pole as can be seen in that equation. The modulator and output stage transfer functions have been split into two sets of equations. The first defines the relationship between the input current and ac reference signal, and the later, define the output stage gain and pole. Due to the nature of a flyback transformer, the gain of the output stage is dependant on the duty cycle (ton/T). For continuous mode operation, the on-time is: ton + N S NP A(dB) = 20 Log10 (A) For example, the voltage divider would be: A+ 5.6 k + 0.0099 560 k ) 5.6 k T @ 2@Vrms Vout )1 Calculating the Loop Gain At this point in the design process, all of the parameters involved in this calculation have been determined with the exception of the pole-zero pair on the output of the voltage error amplifier. All equations give gains in absolute numbers. It is necessary to convert these to the decibell format using the following formula: A(dB) = 20 Log10 0.0099 = -40 dB The gain of the loop will vary as the input voltage changes. It is recommeded that the compensation for the error amplifier be calculated under high line, full load conditions. This should be the greatest bandwidth that the unit will see. By necessity, the unity gain (0 dB) loop bandwidth for a PFC unit, must be less than the line frequency. If the bandwidth approaches or exceeds the line frequency, the voltage error amplifier signal will have freqency components in its output that are greater than the line frequency. These components will cause distortion in the output of the reference amplifier, which is used to shape the current waveform. This in turn will cause distortion in the current and reduce the power factor. Typically the maximum bandwidth for a 60 Hz PFC converter is 10 Hz, and slightly less for a 50 Hz system. This can be adjusted to meet the particular requirements of a system. The unity gain bandwidth is determined by the frequency at which the loop gain passes through the 0 dB level. For stability purposes, the gain should pass through 0 dB with a slope of -20 dB for approximately on decade on either side of the unity gain frequency. This assures a phase margin of greater than 45. The gain can be calculated graphically using the equations of Figure 18 as follows: Divider: Calculate V/Vo in dB, this value is constant so it will not change with frequency. Optocoupler Transfer: Calculate Vfb/Vea using the equation provided. Convert this value into dB. Reference Signal: Calculate Vref/Vfb using the peak level of the ac input signal at high line that will be seen on pin 9. Convert this to dB. This is also a constant value. Modulator and Output Stage: Calculate the gain in dB for DIo/DVref for the modulator, and also the gain in dB for the output stage (DVout/DIin). Calculate the pole frequency. The gain will be constant for all frequencies less than fp. Starting at the pole frequency, this gain will drop off at a rate of 20 dB/decade. Plot the sum of all of the calculated values. Be sure to include the output pole. It should resemble the plot of Figure 45. This plot shows a gain of 34 dB until the pole of the output filter is reached at 3 Hz. After that, the gain is reduced at a rate of 20 dB/decade. http://onsemi.com 30 NCP1651 40 35 30 25 GAIN (dB) 20 15 10 5 0 -5 GAIN (dB) -10 -15 0.01 0.1 10 1 FREQUENCY (Hz) 100 1000 40 20 0 -20 -40 0.01 0.1 1 10 FREQUENCY (Hz) 100 1000 60 cut in half or more and probably remain stable. This can be tested in the circuit, or simulated with a model in SPICE or a similar analysis program. The gain and phase plots of the completed loop are shown in Figures 46 and 47. These include the effects of all of the stages shown. 80 Figure 45. Forward Gain Plot For a crossover frequency of 10 Hz, the error amplifier needs a gain of -25 dB at 10 Hz, since the forward gain is equal to 25 dB at this frequency. The high frequency gain of the error amplifier is: AVhf = Rfb / Rdc1 Where Rdc1 is the output voltage divider resistor that is connected from the output of the converter to the input of the error amplifier. If the output circuit of Figure 42 is used, Rdc1 would be 9.31 k + 453 W, or 9.76 kW. A gain of -25 dB is equal to a divider ratio of: AV = 10(- 25/20) = 0.056 so, Rfb / Rdc1 = 0.056 or, Rfb = 0.056 x 9.76 kW = 546 W The closest standard value resistor is 560 W. To offset the 2 Hz pole of the output filter, the error amplifier should have a zero of 2 Hz or slightly higher. For a 2 Hz zero, the compensation capacitor, Cfb can be calculated by: Cfb + 1 + 95 mF 2 p Rfb 3 Hz Figure 46. Loop Gain Plot -75 -90 -105 PHASE (C) -120 -135 -150 -165 -180 0.01 0.1 1 10 FREQUENCY (Hz) 100 1000 100 mF is the closest standard value capacitor and would be a good choice. This solution will provide a phase margin of close to 90. In practice the value of capacitance could be Figure 47. Loop Phase Plot http://onsemi.com 31 NCP1651 PACKAGE DIMENSIONS SO-16 D SUFFIX CASE 751B-05 ISSUE J 9 -A16 -B1 8 P 8 PL 0.25 (0.010) M B S G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 K C -TSEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S FOOTPRINT FOR SOLDERING 0.060 1.52 0.275 7.0 0.155 4.0 inches mm 0.024 0.6 SO-16 0.050 1.270 The product described herein (NCP1651), may be covered by U.S. patents including 6,373,734. Other patents may be pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 32 NCP1651/D |
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